The present invention relates to the manufacture of semiconductor-on-insulator (SOI) structures using an improved process for making same.
To date, the semiconductor material most commonly used in semiconductor-on-insulator structures has been silicon. Such structures have been referred to in the literature as silicon-on-insulator structures and the abbreviation “SOI” has been applied to such structures. SOI technology is becoming increasingly important for high performance thin film transistors, solar cells, and displays, such as active matrix displays. SOI structures may include a thin layer of substantially single crystal silicon on an insulating material.
Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates. An alternative process includes the bonding of a single crystal silicon wafer to another silicon wafer on which an oxide layer of SiO2 has been grown, followed by polishing or etching of the top wafer down to, for example, a 0.05 to 0.3 micron layer of single crystal silicon. Further methods include ion-implantation methods in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si, in the case of oxygen ion implantation, or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer, as in the case of hydrogen ion implantation.
Manufacture of SOI structures by these methods is costly. The latter method involving hydrogen ion implantation has received some attention and has been considered advantageous over the former methods because the implantation energies required are less than 50% of that of oxygen ion implants and the dosage required is two orders of magnitude lower.
U.S. Pat. No. 7,176,528 discloses anodic bonding processes that produce SOI structures. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween (pressure may also be applied); (iv) cooling the structure to a common temperature; and (v) separating the glass substrate and a thin layer of silicon from the silicon wafer.
After the removal of a first thin layer of silicon (or other semiconductor material) from the donor semiconductor wafer in the SOI process, which may remove less than one micron, about 95% or more of the donor semiconductor wafer may still be available for further use. The re-use of a donor semiconductor wafer has a relatively significant impact on the cost to produce an SOI structure, particularly a large area SOI structure. Donor semiconductor wafer re-use—which may be a dominant factor impacting the process cost—defines how many times a given donor semiconductor wafer can be used during numerous bonding processes to produce SOI structure(s). The re-use factor is even more important when a large area SOI is being produced using separate semiconductor layer structures laterally disposed over a given glass substrate (so-called tiling). For such processes, it is desirable to re-use a given donor semiconductor wafer as many times as possible.
For re-use it is necessary to return a bonding surface of the donor semiconductor wafer to a relatively damage-free state—at least to a state indistinguishable from an un-used (prime surface) of a donor wafer. This has been done by removing a certain thickness of the donor semiconductor wafer, which is contaminated with ions and damaged due to the implantation and exfoliation (separation) processes, by conventional chemical mechanical polishing (CMP) techniques. While CMP techniques are well documented and existing equipment may be readily obtained, there are a number of problems with the existing CMP technology in the context of semiconductor re-use in anodic bonding/exfoliation processes.
Conventional CMP techniques are expensive because, in the case of semiconductor re-use, multiple equipment set-ups are required. A given CMP set-up includes a rotating polishing pad (having certain abrasive characteristics), a slurry (also having certain abrasive characteristics), and a rotating chuck or head to press the semiconductor wafer against the polishing pad and slurry. In accordance with conventional CMP techniques, in order to obtain a semiconductor wafer with satisfactory surface characteristics in a re-use context, multiple polishing pads are needed (see, for example, U.S. Pat. No. 7,510,974). This requires either manual process steps to change the polishing pad on a given piece of equipment, or multiple pieces of equipment, each with a different polishing pad. Either approach adds cost to the manufacturing process and adversely impacts the commercial viability of the SOI structure and end-use application.
Existing CMP polishing protocols call for aggressive removal of material, which increases the risk of depleting the thickness budget for each re-use cycle, and thus increases the risk of missing re-use cost objectives. Concurrently, such aggressive protocols increase the risk of breakage due to associated handling of much thinner (and likely more fragile) wafers.
The conventional CMP protocols do not remove material uniformly across the surface of the donor semiconductor wafer. The state of the art for round semiconductor wafer surface non-uniformities (standard deviation/mean removal thickness) is typically 5-10% of the material thickness removed. As more of the semiconductor material is removed, the variation in the thickness correspondingly worsens. A related problem with conventional CMP processes is that they exhibit particularly poor results when non-round semiconductor wafers (e.g., those having sharp corners, such as rectangular wafers) are polished. Indeed, the aforementioned surface non-uniformities are amplified at the corners of the donor semiconductor wafer compared with those at the center thereof. Multiple re-use of the donor semiconductor wafer by such CMP protocols results in the premature end to a given wafer's re-use life because the surface geometry (e.g., near the corners) exceeds re-use functional limits.
For example, if 0.150 microns of actual damage needs to be removed from a bonding surface of a donor semiconductor wafer, then to be certain that the damaged and contaminated layer has been completely removed from the whole surface (taking into account the aforementioned non-uniform characteristics of the CMP protocols), at least 1.0 micron may be the target thickness for removal. Thus, over five times the thickness of the actual damage is removed in order to be sure that all the damage is removed. This is highly wasteful and has significant, negative cost implications.
Although the manufacturing processes for making SOI structures are maturing, the cost of producing such structures and the final products employing them is driven in part by the ability to use (and re-use) donor semiconductor wafers efficiently. Accordingly, it is desirable to continue to advance the technologies associated with re-using donor semiconductor wafers, such as CMP, in order to control the cost of manufacturing SOI structures.